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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
For a PGAOUT conversion, set CNVST low for a mini-
mum of 30μs or maximum of 40μs. The BUSY output
goes high at the start of the CNVST pulse and the
PGAOUT conversion result is available in the FIFO (if the
ADCMON bit has been set) 52μs (typ) after BUSY goes
low again.
For an ADCIN conversion, set CNVST low for at least
1.5μs. The BUSY output goes high at the end of the
CNVST pulse and the ADCIN conversion result is avail-
able in the FIFO (if the ADCMON bit is set) 7μs (typ) after
BUSY goes low again.
For ease of operation, all CNVST pulses can use a 30μs
width irrespective of the source being converted. In the
case of ADC conversions, the BUSY pulse width is
extended accordingly. For clock modes 00 and 01, the
BUSY pulse width duration depends on the channel con-
version sequence selected.
Continuous conversion is not supported in this clock
mode (see Table 20 for the ADC Conversion register).
Changing Clock Modes During ADC Conversions
If a change is made to the clock mode in the configura-
tion register while the ADC is already performing a con-
version (or series of conversions), the following
describes how the MAX11008 responds:
? When CKSEL = 00 and is then changed to another
value, the ADC completes the already triggered series
of conversions and then goes idle. The BUSY output
remains high until the conversions are completed. The
MAX11008 then responds in accordance with the new
CKSEL mode.
? When CKSEL = 01 and is then changed to another
value and if the device is waiting for the initial external
trigger, the MAX11008 immediately exits clock mode
01, powers down the ADC, and goes idle. The BUSY
output stays low and the new clock mode is observed.
If a conversion sequence has started, the ADC com-
pletes the requested conversions and then goes idle.
The BUSY output remains high until the conversions
are completed. The MAX11008 then responds in
accordance with the new CKSEL mode.
? When CKSEL = 11 and is then changed to another
value and if the device is waiting for an external trig-
ger, the MAX11008 immediately exits clock mode 11,
powers down the ADC, and goes idle. The BUSY out-
put stays low and the new clock mode is observed.
Turning the Continuous Conversion Bit
(CONCONV) On and Off
When switching between continuous and single conver-
sion modes, the clock mode requires resetting to avoid
hanging the ADC sequencing routine.
For example, the following is the command sequence to
switch from continuous to single conversion and revert to
continuous conversion:
1) Write ADCCON (00000000 10110111).
2) Turn off the selected channels, but leave the continu-
ous convert bit asserted. Write ADCCON (00000000
10000000).
3) Turn off the continuous convert bit. Write ADCCON
(00000000 00000000).
4) Change from the current clock mode (00 in this case)
to any other one. Write HCFIG (00000100 00011000).
5) Change the clock mode back. Write HCFIG
(00000100 00001000).
6) Clear the FIFO. Write SCLR (00000000 00000100).
7) Perform the single conversion. Write ADCCON
(00000000 00110111).
8) Read the FIFO five times to capture the results of the
single conversions. Read FIFO.
9) Turn continuous convert back on. Write ADCCON
(00000000 10110111).
The alternative to this command sequence is to leave
continuous conversion on and just read the FIFO. When
using this method, decode the channel tag to determine
which channel has been read.
12-Bit DACs
In addition to the 12-bit ADC, the MAX11008 also
includes two voltage-output, 12-bit, monotonic DACs
with typically less than ±2 LSB integral nonlinearity
error and less than ±1 LSB differential nonlinearity
error. Each DAC also has a 45ms settling time and
ultra-low glitch energy (4nV·s). The 12-bit DAC codes
are unipolar binary with 1 LSB = V REFDAC /4096.
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